In U.S. Pat. No. 4,321,486 of Clifford H. Boler and myself and assigned to the assignee of the present invention, a system is described for use in autofocus cameras particularly of the through the lens type such as is found in the U.S. Pat. No. 4,333,007 of Richard A. Langlais, Francis T. Ogawa, and myself and also assigned to the assignee of the present invention.
Such systems operate utilizing a plurality of light sensitive detectors which are normally of the CCD type arranged in pairs behind a plurality of lenslets so as to receive an image of the exit pupil of the taking lens that receives light from the remote subject to be focused upon. If the taking lens is at the correct focal position, the outputs of the two detectors behind each lenslet will be substantially the same, but as the taking lens moves from the desired focal position, differences in the outputs of the two detectors behind each lenslet will occur in such a manner that the system may determine the direction and amount of movement necessary to bring the taking lens back to the proper focal position. In the circuitry of the prior art, a clock phase generator is employed to drive a shift register and a microprocessor operating through a bus control and an R-S flip-flop, operates to produce a "start" signal in synchronism with the clock to activate the detectors. The detectors then begin the process of integrating the light they receive. After a short period of time which depends normally upon the intensity of light being received, the clock operates to activate a transfer gate which then dumps the built-up charges on the individual detectors in parallel into the shift register. The shift register produces these signals in series to the microcomputer so that they may be analyzed to determine the correct output for proper focus.
Because the shift register is driven by the clock producing 3 phases, .phi..sub.1, .phi..sub.2, and .phi..sub.3, there are only predetermined times available when the charges from the detector may be dumped into the shift register (for example, upon the occurrence of a .phi..sub.1 signal). When it is desired to "start" the detectors, the microprocessor through the bus control produces a signal, this signal is usually the removal of a voltage to the reset terminal of an R-S flip-flop to cause resetting thereof. The set terminal of the flip-flop is connected to the clock so that after reset, the next .phi..sub.1 of the clock causes the flip-flop to produce an output to activate the detectors. At the end of the desired integrating period, a signal from the microprocessor causes the clock to produce a transfer signal, at the next .phi..sub.1, directly to the transfer gate which then dumps the charges from the detectors into the shift register.
In the system described above, the switching on and off must be done in synchronism with the clock, and as will be more fully discussed hereinafter in connection with FIG. 1, this produces a problem when very high intensities of light are encountered. Since, as mentioned above, the flip-flop is triggered by the falling edge of one of the three phases of the clock, the detectors can only be activated at one of these three times in a cycle. Likewise, since the shift register can only receive the charges from the detectors at the predetermined times (for exmaple the falling edge of .phi..sub.1), the transfer gate can be activated only then. Therefore, the minimum time period between activation of the detectors and dumping the charges into the shift register can be no shorter than the time from one falling edge of a signal from the clock to the next time the shift register is capable of receiving the next group of charges, i.e., the time between the two consecutive .phi..sub.1 's. This time period, although very short, may be still too long in the event of high intensities of light and the detectors may saturate and thus loose the significance of their charges during that short time period. Furthermore, there is no way to vary the exposure time of the detectors between the occurrences of all three phases.